RL-based floorplans for next-gen TPUs

Google AI researchers Azalia Mirhoseini and Anna Goldie published a Nature paper on their AI-powered computer chip design methodology, which uses “an edge-based graph convolutional neural network architecture capable of learning rich and transferable representations of the chip.” Trained on a dataset of 10,000 chip floorplans, the method replaces “months of intense effort” for humans, and comes up with a more optimal end result. I covered this research when it first came out in April 2020, but the big news now is that it has been productionized: Mirhoseini and Goldie have used it to design the next generation of Google’s Tensor Processing Units (TPUs)!